IBM Unveils First Sub-1nm Chip With 100 Billion Transistors

IBM on June 25, 2026, took the wraps off what it is calling the world’s first sub-1 nanometer chip technology, a research-stage breakthrough that promises to push the semiconductor industry well past a barrier that many in the field thought was still years away.

Unveiled at IBM’s Yorktown Heights research labs, the new design uses a 3D transistor architecture the company has nicknamed "nanostack" and pegs it at the 0.7 nm — or 7 angstrom — node. In modern chip terminology, these labels are more about generation than literal dimensions, but the upshot is clear: this is the first time anyone has demonstrated a transistor architecture branded below the 1-nanometer line.

The new design packs roughly 100 billion transistors onto a die about the size of a fingernail, IBM said. By stacking and staggering transistors vertically rather than relying solely on shrinking them horizontally, the architecture takes advantage of what engineers call 3D sequential integration — essentially building skyscrapers of logic instead of squeezing more houses onto one block.

That matters because traditional chip scaling, summed up for decades by Moore’s Law, has been running into the hard ceiling of atomic physics. Standard transistors are now so small that further shrinks bring diminishing returns and rising leakage, heat, and manufacturing cost. IBM’s nanostack tries to sidestep that wall by going up instead of in, layering transistors on top of one another with new materials and process steps designed to keep electrical performance intact.

In its announcement, IBM described the architecture as one that "will propel the semiconductor industry forward for the next decade and beyond." The company has long played an oversized role in chip research relative to its size in commercial manufacturing — its labs pioneered FinFET and gate-all-around designs that are now industry standard, but those innovations were typically commercialized by partners like Samsung, Intel, and the foundries that supply Apple, NVIDIA, and others.

The same is likely to happen here. IBM is positioning nanostack as a research platform that future commercial fabs will license and build on, rather than something it will produce itself in volume. The company already has a track record of doing exactly that with the 2 nm test chip it announced in 2021, which became a stepping stone for the next generation of high-performance processors.

The implications, if the technology makes it to production, are substantial. A roughly 100-billion-transistor chip would be a major step up from today’s leading-edge processors and would give chip designers more headroom to support increasingly demanding workloads — especially the large AI models that have driven a global scramble for compute capacity. More transistors per area also tend to translate into better energy efficiency, which has become a growing concern as data centers expand and AI training runs balloon in cost.

There are still significant questions to be answered. Sub-1-nanometer process nodes will require advances across the entire semiconductor stack, from extreme ultraviolet (EUV) lithography tools to new materials and chemicals, and from packaging to thermal management. IBM did not announce a commercial timeline, and any production-grade nanostack chips are likely several years out.

For now, though, the announcement is a milestone in its own right. After years of headlines warning that Moore’s Law was running out of room, IBM has handed the industry a credible 3D recipe for keeping the transistor count climbing well past once-feared physical limits. The next chapter of chip design just got a lot more interesting.